1. Field of the Invention
The invention relates to a circuit arrangement in a picture display device, comprising a video signal processing circuit for an incoming video signal and a line synchronizing circuit for generating a reference signal for the horizontal scanning on a picture display screen, a signal generator for generating the reference signal and a clock signal for the video signal processing circuit, and a phase control loop for controlling the signal generator, said phase control loop comprising a phase discriminator circuit having a first input for receiving a line synchronizing signal which is present in the incoming video signal, a second input for receiving the reference signal and an output which is coupled to a loop filter and to a control input of the signal generator for applying a control signal to said input, the reference signal having the same frequency and substantially the same phase as the line synchronizing signal in the synchronous state of the control loop, and the clock signal frequency being coupled to the frequency of the reference signal.
2. Description of the Related Art
Such a circuit for processing video signals, for example, colour television signals, is proposed in the non-prepublished Netherlands Patent Application 8801415 (PHN 12.586) corresponding to U.S. Pat. No. 4,926,280. The video signal processing circuit described in this Application is a digital circuit with a clock signal for sampling, storing, processing and reading the video information. The frequency of the clock signal is coupled to the frequency of the reference signal so that samples of successive lines are displayed one below the other on the display screen, with the advantage that said processing operations of the video information, for example, interpolation are effected in a simple manner.
However, it has been found that even at a line frequency which has remained constant, the frequency of the reference signal may be disturbed, namely during the occurrence of the pulses which are present in the line synchronizing signal. In fact, in the synchronous state of the phase control loop, the output signal of the phase discriminator has a given polarity during the first half of a line synchronizing pulse with respect to a substantially constant value which this signal has between the pulses, and this signal has the other polarity during the second half of the pulses. After the pulse said signal assumes the same value as before. In the non-synchronous state of the phase control loop the disturbance is also present, be it that the value of the signal after the occurrence of the pulse is not equal to the value before it, so that the frequency and/or the phase of the oscillator are controlled. It is apparent therefrom that the control signal has a ripple resulting in a variation of the frequency and hence of the phase of the reference signal. If there is no phase difference between the signals at the inputs of the phase discriminator, this phase shift is exactly zero over one line period. Said disturbance is described, for example, in Netherlands Patent Application 8702538 (PHN 12.303).
In many applications of such line phase control loops, the above-mentioned disturbance is not a noticeable impediment, but in high-quality picture display devices, the disturbance may cause a display error which is unacceptable. In fact, the video information processing operations introduce delays, with the result that the video information can also be read during the occurrence of the line synchronizing pulses in the incoming video signal, in which period the clock is thus disturbed. For example, if the requirement is imposed that the phase shift caused by the disturbance and expressed in time must be smaller than 5 ns during a line period, it appears that conventional line phase control loops cause a larger disturbance, for example, approximately 14 ns in the case of the integrated circuit TDA 2579 of Philips, and they are therefore not readily usable.
The disturbance may be reduced by choosing a larger time constant for the line phase control loop, but this results in a poorer behavior of the loop during lock-in. The detrimental effect of the disturbance can be prevented by ensuring that video information cannot be read during the occurrence of a line synchronizing pulse. However, this requires an extra memory. The circuit described in Netherlands Patent Application 8203556 corresponding to U.S. Pat. No. 4,574,307 has a switch-over facility with which the reference signal is controlled to the leading edge of the line synchronizing pulse in the synchronous state of the control loop. In this case the disturbance is supplied by the reference signal and it is smaller as the pulse in this signal is shorter. Its drawbacks are a poorer noise behavior, because the control information is given by only one edge of the synchronizing pulse, and the phase error which is produced during switching. Another possibility is to sample the control signal first and retain it for one line period so that a constant control signal for the signal generator and hence a fixed frequency are obtained. However, since the phase error is determined only once per line, the control loop has already a sampling character. It is found that this second sampling operation changes a second-order loop to a third-order loop, which results in a very poor step response, particularly in fast loops. It starts to oscillate in an unacceptable way.